1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and in particular, relates to a semiconductor device and a method for manufacturing a semiconductor device in which variations are reduced and characteristics are improved.
2. Description of Related Art
In semiconductor processes after the 90 nm generation, variations in transistor characteristics like Ion (on-state current)/Vth (threshold voltage) of a MOS (Metal-Oxide Semiconductor) transistor are greatly developed due to miniaturization of elements. As a result, there is a situation where variations in transistor characteristics greatly affect a performance yield at an LSI (Large-Scale Integration) manufacturing stage. Additionally, great variations in transistor characteristics have to be coped with at an LSI circuit designing stage, leading to lengthening of a designing period and increase of development costs. As mentioned above, great increase in variations in transistor characteristics is a great barrier in LSI designing and manufacturing.
In particular, random variations greatly concerned with variations in transistor characteristics, have become a great dominating factor as a process of the miniaturization generation advances. For this reason, various companies involved in semiconductor manufacturing report some investigations of random variations, trial production and proposals aimed at reduction in random variations, as shown in, for example, the non-patent literature 1, 2, 3, and 4. Here, the non-patent literature 1 is: F. Arnaud et al., “Competitive and Cost Effective high-k based 28 nm CMOS Technology for Low Power Applications” in IEDM Tech. Dig, 2009. The non-patent literature 2 is: M. J. M Pelgrom et al., “Matching Properties of MOS Transistors” in IEEE Solid-State Circuits, p. 1433, 1989. The non-patent literature 3 is: K. Takeuchi et al, “Understanding Random Threshold Voltage Fluctuation by Comparing Multiple Fabs and Technologies” in IEDM. Tech. Dig., 2007. The non-patent literature 4 is: K. Takeuchi et al, “Single-Charge-Based Modeling of Transistor Characteristics Fluctuations Based on Statistical Measurement of RTN Amplitude” in VLSI Symp. Tech. Dig., 2009.
It is known that random variations are expressed by a criteria expression as represented by the Pelgrom plot (the non-patent literature 2 and 3). According to the criteria expression, random variations depend on an Lg dimension (gate length), a Wg dimension (gate width), a Tinv (thickness of an inversion layer; equivalent oxide thickness), and an Nsub (an impurity concentration under a gate) of a transistor. In recent years, the Takeuchi plot, which is further standardized from the above criteria expression, has been reported (the non-patent literatures 3 and 4). According to the criteria expression of the Takeuchi plot, random variations depend not only on a Lg, a Wg, and a Tinv as mentioned above, but also on a Vth and a Vfb (flat band voltage).
In view of the dependence tendency shown by the above criteria expressions, random variations keep on increasing as an Lg dimension and a Wg dimension of a transistor shrink due to the advancement of miniaturization. However, increase in random variations can be prevented since a Tinv is reduced (thinned) as a result of the advancement of miniaturization.
However, the number of transistors provided in an LSI is greatly increased due to the advancement of the miniaturization technology. In a case of an SRAM macro therefore, it is necessary to anticipate greater random variations σ (standard deviations) which follow normal distribution as a premise, compared with a case of a previous generation. As a result, there is a risk that reduction in operation margins and reduction in yields in terms of circuit design occur. For the miniaturization generation of the recent years therefore, a method for reducing random variations with factors other than a Tinv is desired. Additionally, it is desirable that fluctuation in characteristics and degradation of performance due to the reduction in random variations should be avoided at the same time.
As a related technique, Japanese Patent Publication JP-P2006-59843A (the patent literature 1) discloses a semiconductor device and a method for manufacturing the semiconductor device. The object is to control diffusion of boron in extension portions of source/drain regions in a PMOSFET, so that short-channel effect can be controlled and operation of a more miniaturized PMOSFET can be secured. The semiconductor device has an n-well region, a gate electrode, boron diffusion regions, diffusion regions with diffusion controlling elements, and a p-type impurity diffusion region. The n-well region is formed in a semiconductor substrate. The gate electrode is formed on the n-well region. The boron diffusion regions are formed in a surface layer of the n-well on the both ends of the gate electrode. The diffusion regions with diffusion controlling elements, in which at least one kind of diffusion controlling elements selected from a group of fluorine, nitrogen and carbon, is diffused, include the boron diffusion regions at least in a lateral direction under the gate electrode from the boron diffusion layers. The p-type impurity diffusion region is positioned deeper than the boron diffusion regions so that the ends in a lateral direction are separated farther from the end of the gate electrode than the ends in a lateral direction of the boron diffusion region.
As a related technique, Japanese Patent Publication JP-P2006-121025A (the patent literature 2; US2006068556 (A1)) discloses a semiconductor device and a method for manufacturing the semiconductor device. The object is to control short-channel effect with steep and shallow junction of an impurity concentration profile in a channel diffusion layer, and maintain high drive force with a low-resistance channel diffusion layer having a sufficient activation concentration. The semiconductor device includes a gate insulating film, a gate electrode, and a channel diffusion layer. A gate insulating film is formed on a semiconductor region of a first conductivity type. The gate electrode is formed on the gate insulating film. The channel diffusion layer, which is a first conductivity type, is formed below the gate electrode in the semiconductor region. The channel diffusion layer includes carbon as impurities.
Japanese Patent Publication JP-P2009-272423A (the patent literature 3; US2009278209 (A1)) discloses a semiconductor device and a method for manufacturing the semiconductor device. The object is to achieve shallow junction and low resistance of extension diffusion layers following miniaturization, and achieve a miniaturized device having high drive force. The semiconductor device includes a gate electrode, extension diffusion layers, and source/drain diffusion layers. The gate electrode is formed on a semiconductor region, with a gate insulating film therebetween. The extension diffusion layers, in which first impurities of a first conductivity type are diffused, are formed on both sides of the gate electrode in the semiconductor region. The source/drain diffusion layers are positioned outside the extension diffusion layers in the semiconductor region and the junction depth of the source/drain diffusion layers is deeper than that of the extension diffusion layers. The extension diffusion layers include carbon on at least one of the both sides of the gate electrode.
Japanese Patent Publication JP-P2009-60130A (the patent literature 4; US2006068556 (A1)) discloses a semiconductor device and a method for manufacturing the semiconductor device. The object is to control short-channel effect with steep and shallow junction of an impurity concentration profile in a channel diffusion layer, and maintain high drive force with a low-resistance channel diffusion layer having a sufficient activation concentration. The semiconductor device includes a gate insulating film, a gate electrode, extension diffusion layers, and pocket diffusion layers. The gate insulating film is formed on a semiconductor region of a first conductivity type. The gate electrode is formed on the gate insulating film. The extension diffusion layers, which are a second conductivity type, are formed under the sides of the gate electrode in the semiconductor region. The pocket diffusion layers, which are a first conductivity type, are formed under the extension diffusion layers in the semiconductor region, in contact with the extension diffusion layers. The pocket diffusion layers include carbon as impurities.
Japanese Patent Publication JP-A-Heisei 10-125916 (the patent literature 5) discloses a semiconductor device and a method for manufacturing the semiconductor device. The object is to miniaturize a transistor while having a precise threshold voltage, by providing a means to prevent expansion in a depth direction of such an impurity diffusion layer as a source/drain region. The semiconductor device includes a semiconductor substrate, a substrate region, a gate insulating film, a gate electrode, source/drain regions, and carbon-doped regions. The substrate region, which is a first conductivity type, is formed in the semiconductor substrate. The gate insulating film is formed on the semiconductor substrate. The gate electrode is formed on the gate insulating film. The source/drain regions, which are a second conductivity type, are formed in regions positioned on the both sides of the gate electrode in the semiconductor substrate. The carbon-doped regions are formed in regions which at least overlap the source/drain regions.
WO2007/096976 (the patent literature 6; US2008277733 (A1)) discloses a semiconductor device and a method for manufacturing the semiconductor device. The semiconductor device includes a semiconductor substrate, a gate electrode, source and drain extension regions, a first piezoelectric material pattern, a second piezoelectric material pattern, and source and drain regions. The gate electrode is formed on the semiconductor substrate. The source and drain extension regions are formed on first and second sides which correspond to first and second sidewall surfaces of the gate electrode respectively, in the semiconductor region. The first piezoelectric material pattern covers the semiconductor substrate continuously from the first side of the gate electrode to the first sidewall surface of the gate electrode. The second piezoelectric material pattern covers the semiconductor substrate continuously from the second side of the gate electrode to the second sidewall surface of the gate electrode. The source and drain regions are formed outside the source and drain extension regions, in the semiconductor substrate. Pocket implantation regions are formed to overlap the source and drain extension regions. Pocket implantation is performed by adding nitrogen, fluorine, and carbon for example when needed.
The inventors have now discovered the following facts.
The inventors have now found that addition of a C (carbon) factor into a Halo implantation process is effective in addition to a method where a Tinv is thinned, as a method for reducing random variations in an NMOS transistor. As an example, a semiconductor device, with which the effect is proven by the inventors, will be described below.
FIG. 1 is a sectional view showing an example of a configuration of a semiconductor device with which effect is proven by the inventors. A semiconductor device 2 is an NMOS transistor, which is one of the NMOSFETs (N-channel Metal Oxide Semiconductor Field Effect Transistor), has a channel region 20, extension regions 26, source/drain regions 21, halo regions 27, a gate insulating film 23, a gate electrode 22, offset spacers 24, and sidewalls 29.
The channel region 20 is formed in a surface layer of a semiconductor substrate. The extension regions 26 are formed on the both ends of the channel region 20, in the surface layer of the semiconductor substrate. The source/drain regions 21 are formed at the ends of the extension regions 26, opposite to the channel region 20, in the surface layer of the semiconductor substrate. The halo regions 27 are formed under the extension regions 26 in the semiconductor substrate. The gate insulating film 23 is formed on the channel region 20. The gate electrode 22 is formed on the gate insulating film 23. The offset spacers 24 are formed to the side surfaces of the gate electrode 22. The sidewalls 29 are formed to the side surfaces of the offset spacers 24, on the extension regions 26. In the channel region 20, a channel impurity region 25 in which impurities (e.g. boron) are doped, is formed. Carbon is implanted from the surface of the semiconductor substrate including the extension regions 26 and the halo regions 27, to inside regions 28. Additionally, carbon is implanted from the channel region 20 including the channel impurity region 25, to an inside region 28a. 
FIG. 2 is a flow diagram showing a method for manufacturing the semiconductor device in FIG. 1. First, a diffusion layer is formed in a predetermined region in the surface layer of the semiconductor substrate (step S31). Next, channel implantation is performed into the channel region 20 to form the channel impurity region 25, in order to control a threshold voltage Vth (step S32). Next, the gate insulating film 23, which is a SiON (silicon oxynitride) film, is formed on the channel region 20 (step S33). At this time, the gate insulating film may be a SiO2 (silicon oxide) film. After that, the gate electrode 22 is formed of Poly-Si (polysilicon) (step S34). Next, after forming the offset spacers 24, the halo regions 27 are formed by performing halo implantation (step S35) and the extension regions 26 are formed by performing extension implantation (step S36) for the purpose of overlap adjustment under the gate (suppressing of the short channel effect). After that, the sidewalls 29 are formed (step S37), and source/drain implantation is performed to form the source/drain regions 21 (step S38).
The implantation factors of the channel implantation, the halo implantation, and the extension implantation used for the steps S32, S35, and S36, are B (boron), BF2 (boron difluoride), and As (arsenic), respectively. The implantation condition of B is: 12 keV, 4×10+12−12×10+12/cm2; the implantation condition of BF2 is: 29 keV, 4.8×10+13/cm2, 15 degrees; and the implantation condition of As is: 7 keV, 5×10+14/cm2, respectively. At this time, P (phosphorus) instead of As, and B (boron) instead of BF2, may be used. Note that the above implantation conditions are just one example, and conditions used in a CMOS process flow in each generation are possible. Additionally, other steps may be the same as the ordinary CMOS process flow.
The improvement method by the inventors is different from an ordinary CMOS process flow, in that carbon implantation (step S41) is applied before halo implantation when the halo implantation (step S35) is performed. In the carbon implantation (step S41), an implantation condition of C (carbon) is: 7 keV and 5×10+14/cm2. It is preferable that the C implantation condition should be an energy condition which corresponds to an active B depth under a transistor formed by halo implantation. It is also preferable that a dose of C should be two times or over two times the total of a dose of B at channel implantation and a dose of B at halo implantation. At this time, C implantation may be applied after halo implantation.
Characteristics of an NMOS transistor manufactured by using the above manufacturing method will be described.
FIG. 3 is a graph showing the relationship between a random variation in a threshold voltage Vth and a dose of B of channel implantation. A vertical axis and a horizontal axis show a random variation in a threshold voltage Vth (standard deviation σ (Vth)) and a dose of B of channel implantation (Channel Dose), respectively. FIG. 4 is a graph showing the relationship between a random variation in a threshold voltage Vth and a threshold voltage Vth. A vertical axis and a horizontal axis show a random variation in a threshold voltage Vth (σ(Vth)) and a threshold voltage Vth, respectively. In FIG. 3 and FIG. 4, diamonds and a solid line connecting the diamonds, show a case where C implantation (step S41) is not applied at the time of halo implantation (step S35). Squares and a broken line connecting the squares show a case where C implantation (step S41) is applied at the time of halo implantation (step S35). In the manufacturing method, process conditions are the same for each NMOS transistor, excluding a dose of B of channel implantation and application of C implantation. As for the dimensions of the measured NMOS transistor, an Lg (gate length) is 60 nm; and a Wg (gate width) is 100 nm.
As shown in FIG. 3, the case where C implantation is applied (squares/broken line) and the case where C implantation is not applied (diamonds/solid line) are compared, with the same channel dose condition. It is understood that the random variation σ (Vth) in a threshold voltage Vth is reduced approximately by 20% by applying the C implantation. For example, when a channel dose condition is 10×10+12/cm2, σ (Vth) is reduced approximately by 22% from about 45 mV to about 35 mV, by applying the C implantation.
As shown in FIG. 4, the case where C implantation is applied (squares/broken line) and the case where C implantation is not applied (diamonds/solid line) are compared, with the same threshold voltage Vth. It is understood that the random variation σ (Vth) in a threshold voltage Vth is reduced approximately by 20% by applying the C implantation. For example, when a threshold voltage Vth is 400 mV, σ (Vth) is reduced approximately by 20% from about 41 mV to about 33 mV, by applying the C implantation.
As shown by the above tendencies, it has been revealed that random variations can be reduced by applying the C implantation (step S41) to the halo implantation (stepS35). However, further research by the inventors has revealed that the following problem occurs when C implantation is performed. FIG. 5 is a graph showing the relationship between a threshold voltage Vth and a dose of B of channel implantation. A vertical axis and a horizontal axis show a threshold voltage Vth and a dose of B of channel implantation (Channel Dose), respectively. FIG. 5 is a graph in which FIG. 3 and FIG. 4 are combined. As shown in FIG. 5, the case where C implantation is applied (squares/broken line) and the case where C implantation is not applied (diamonds/solid line) are compared, with the same channel dose condition. It is understood that a threshold voltage Vth is lowered by applying the C implantation, under the same channel dose condition. Therefore, it is necessary to improve a shifted (lowered) threshold voltage Vth to a desired value in some way.
As a method for improving a shifted threshold voltage Vth, a method can be considered in which a dose of B is made to be higher in the channel implantation. From the Pelgrom plot mentioned above, it is generally known that random variations in a threshold voltage Vth depend on an Nsub under a gate (an impurity concentration under a gate). Therefore, an Nsub (an impurity concentration under a gate) is naturally increased as a dose of B of the channel implantation is increased. As a result, there is a problem that random variations are increased accordingly.
As a method for improving a shifted threshold voltage Vth, a method can also be considered in which a dose of BF2 (or B) is made to be higher in the halo implantation. When a dose of BF2 (or B) is made to be higher in the halo implantation however, an Nsub (an impurity concentration under agate) is increased. As a result, random variations are increased accordingly. At the same time, it is concerned that an off-leakage component of a transistor possibly increases since a GIDL (Gate Induced Drain Leakage) component and a JL (Junction Leakage) component are also increased. For this reason, a method which can control a threshold voltage Vth without increasing an impurity concentration under a gate, is required.
It is considered that the reducition of random variations as a result of the application of the C implantation is attributed to control of TED (Transient Enhanced Diffusion) of B by a C factor, and to suppress a tendency for B to increase in high concentration under a channel, as shown in the patent literatures 1 to 5. It has been proved that random variations in a threshold voltage Vth are generally greater in NMOSs than in PMOSs (the non-patent literature 3).
A technique which can reduce random variations in transistors and control transistor characteristics at desired values is desired.